1. Field of the Invention
The present invention relates to a flash memory device which improves a speed of reading data of a mass storage flash memory, and more particularly to a flash memory device that solves a problem of losing data due to data collision even in the fast data reading operation.
2. Description of the Conventional Art
FIG. 1 illustrates a conventional flash memory which includes a memory array 1 consisting of a plurality of flash memory cells, a sense amp unit 2 amplifying data stored in a selected cell of the memory array 1 or amplifying externally inputted data to store in a selected cell, a data buffer 3 storing the data amplified by the sense amp unit 2 or storing the externally inputted data, an input/output buffer 4 storing data or an address inputted through an input/output pad or storing data from the data buffer 3, a row buffer 5 storing row addresses among addresses inputted through the input/output buffer 4, a row decoder 6 decoding the row addresses which are inputted to the row buffer 5 and thus selecting word lines of the memory array 1, a column decoder 7 decoding column addresses among the addresses inputted through the input/output buffer 4 and thus selecting bit lines of the memory array 1, and a control unit 8 controlling each of the above blocks.
FIG. 2 is a detailed block diagram of the control unit 8. As shown therein, the control unit 8 includes a first counter 8a performing up-counting to connect the m number of column lines to the data buffer 3 by being synchronized with an external clock signal CLK, a second counter 8b synchronized with the external clock signal CLK and receiving a carry of the first counter for thereby performing the up-counting to select the n number of word lines of the data buffer 3, a counter control unit 8e receiving the external clock signal CLK and a counter enable signal CNTEN and controlling the first and second counters 8a, 8b, a first decoder 8c receiving an output from the first counter 8a and connecting the m number of the column lines to the data buffer 3, and a second decoder 8d receiving an output from the second counter 8b and selecting the n number of the row lines of the data buffer 3.
The operation of such conventional flash memory will be described with reference to the accompanying drawings. In order to promptly operate the mass storage flash which synchronizes the input/output of the data to the external clock signal CLK, the data buffer 3 is connected between the memory array 1 and the input/output buffer 4, the data buffer 3 storing information of one word line of the memory array 1.
In a read mode, a word line of the memory array 1 which is to be read is selected and data stored in a cell connected to the selected word line are amplified by the sense amp unit 2 and stored in the data buffer 3 which is then synchronized with the external clock CLK and outputs the data stored therein to an external circuit through the input/output buffer 4.
Referring to FIG. 3, the process of reading data of the memory array 1 will be explained in detail.
First, the sense amp unit 2 amplifies the data stored in cells of the memory array 1 and transmits the data to the data buffer 3. Then, the counter enable signal CNTEN at a high level, as shown in FIG. 3B, is applied to he counter control unit 8e, and after a predetermined time which is about 100 .mu.s the external clock CLK shown in FIG. 3A is applied thereto. Accordingly, the counter control unit 8e outputs a reset-off signal RSTOFF as in FIG. 3C at the point where the external clock CLK is applied, for thereby enabling the first and second counters 8a, 8b, and the first decoder 8c sequentially outputs column selection signals, as shown in FIGS. 3D, 3E and 3F to the data buffer 3 in accordance with a signal outputted from the first counter 8a.
Here, the reset-off signal RSTOFF is outputted from the counter control unit 8e and the second decoder 8d enables the row selection signal at the high level, as shown in FIG. 3G, and then enables the next row selection signal as in FIG. 3H when the read operation of the data buffer 3 is completely finished. That is, while a first row of the data buffer 3 is selected by the row selection signal shown in FIG. 3G, the first decoder 8c sequentially outputs the column selection signals, as shown in FIGS. D, E and F, thereby externally outputting the data shown in FIG. 3J. Then, as shown in FIG. H, after a second row is selected, the first decoder 8c sequentially outputs the column selection signals by the above described operation, thereby suceedingly outputting the data of the data buffer 3. Thus, the data of the data buffer 3 are synchronized with the external clock CLK, thus performing the reading operation.
However, in the conventional art, since data which are stored in the data buffer are read and outputted by being synchronized with the external clock signal, there is a limit to increase the speed of reading data unless making the external clock signal fast, which may have a problem of losing the data due to the data collision.